1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly, to eliminating dishing non-uniformity of a process layer, formed above a surface of a wafer.
2. Description of the Related Art
CMP is a widely used means of planarizing silicon dioxide as well as other types of processing layers on semiconductor wafers. Chemical mechanical polishing typically utilizes an abrasive slurry disbursed in an alkaline or acidic solution to planarize the surface of the wafer through a combination of mechanical and chemical action. Generally, a chemical mechanical polishing tool includes a polishing device positioned above a rotatable circular platen or table on which a polishing pad is mounted. The polishing device may include one or more rotating carrier heads to which wafers may be secured, typically through the use of vacuum pressure. In use, the platen may be rotated and an abrasive slurry may be disbursed onto the polishing pad. Once the slurry has been applied to the polishing pad, a downward force may be applied to each rotating carrier head to press the attached wafer against the polishing pad. As the wafer is pressed against the polishing pad, an exposed surface, i.e., polishing surface, of a process layer formed above a surface of the wafer is mechanically and chemically polished.
As semiconductor devices are scaled down, the importance of chemical mechanical polishing to the fabrication process increases. In particular, it becomes increasingly important to control and minimize within-wafer topography variations, i.e., it is desirable for a post-polish surface of a process layer to be as planar as possible. Moreover, depending upon the particular process, if a post-polish surface of a process layer is not sufficiently planar, subsequent processing steps may be undesirably affected. For example, in one embodiment, to minimize spatial variations in downstream photolithography and etch processes, it is necessary for the thickness of an oxide layer, formed above a surface of a wafer, to be as uniform as possible
Those skilled in the art will appreciate that a variety of factors may contribute to producing surface non-uniformity, such as dishing, in a process layer. In one embodiment, a process layer may be formed above a surface of a substrate, e.g., a wafer, or a previously formed process layer. During formation, the process layer may conform to the topography of the substrate and, if the surface of the substrate is non-uniform, the process layer may exhibit the same type of surface non-uniformity. For example, if the surface of the substrate is dished, a corresponding surface of the process layer may also be dished.
Typically, CMP is used to planarize a non-uniform polishing surface of a process layer, i.e., CMP may be used to reduce surface variations in a pre-polish surface of the process layer. For example, CMP may be used to remove or at least partially reduce the severity of dishing non-uniformity of the process layer. In one embodiment, during a polishing process, the thicker portions of the process layer may shield the dished areas of the process layer from the polishing pad, and as a result, the polish removal rate may be greater for the thicker portions of the process layer as compared to the dished areas. This difference in polish removal rate may be used, during the polishing process, to produce a more planar post-polish surface of the process layer.
Unfortunately, with severe surface non-uniformity, e.g., severe dishing of the process layer, conventional CMP may not be capable of adequately planarizing the polishing surface of the process layer. For example, the dished portions of the process layer may be too severe to be corrected by changes in the polish removal rate. Moreover, the slurry used during the polishing process may react with the entire polishing surface of the process layer, and the thinner dished portions of the process layer may be at least partially abraded by the chemical action of the slurry, even though shielded from the polishing pad by the thicker portions of the process layer. Depending upon the application, any residual uncorrected non-uniformity remaining on a post-polish surface of a process layer may contribute to impaired final device performance or complete device failure.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
In one aspect of the present invention, a method is provided. The method includes providing at least one wafer having a process layer formed thereon. A surface of the process layer is polished using a first polishing process that is comprised of a slurry and a first polishing pad. The slurry is removed from the surface of the process layer. The surface of the process layer is planarized using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad.
In another aspect of the present invention, a system is provided. The system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon. The polishing tool is a adapted to polish a surface of the process layer using a first polishing process that is comprised of a slurry and a first polishing pad and remove the slurry from the surface of the process layer. The polishing tool is adapted to planarize the surface of the process layer using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. The process controller is coupled to the polishing tool and is adapted to communicate with at least one of a slurry controller and the polishing tool.